Many semiconductor devices include peripheral regions with relatively larger peripheral features (e.g., control circuitry) and array regions with relatively smaller array features (e.g., memory cells). During the manufacture of such semiconductor devices, both the peripheral regions and array regions are often planarized simultaneously, such as by performing an abrasive planarization operation in the form of a chemical-mechanical planarization (CMP) operation. For example, in forming a phase change memory (PCM) device, array features are formed in the array region, after which material used to form the array features (e.g., cell material) is removed from the peripheral region. A filler material is formed in the peripheral region, and both the peripheral region and array region are planarized through a single CMP operation in preparation for forming some of the peripheral features.
Due to non-uniformity in thickness of the filler material in the peripheral region, non-uniformity in thickness of the array region and the peripheral region prior to the CMP operation, there is a significant risk of the CMP operation removing too much or too little material in the array region. For example, removing too much material in the array region may damage the array features, resulting in contamination of memory cell material, and causing performance failures. In addition, removing too much material in the array region may result in unwanted electrical shorts between the array features, which also causes performance failures. Similar defects and failures may be a result of removing too little material in the array region. Thus, improvements in uniformity of planarization in the manufacturing of semiconductor devices are desired.